(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create an insulator filled shallow trench, isolation region.
(2) Description of the Prior Art
The semiconductor industry is continually striving to increase the performance of semiconductor devices, while still attempting to maintain, or decrease, the processing cost of these same semiconductor devices. The ability to fabricate semiconductor devices with sub-micron features, or the use of micro-miniaturization, has allowed these performance and cost objectives to be partially realized. The use of sub-micron features, allow performance degrading, parasitic capacitances, to be reduced, resulting in higher performing semiconductor devices. In addition the use of sub-micron features, allow smaller semiconductor chips to be created, however still possessing device densities comparable to larger semiconductor chip counterparts, fabricated without the use of sub-micron features. The use of smaller semiconductor chips in turn result in the attainment of a greater number of chips to be achieved from a specific size starting substrate, thus reducing the processing cost of a specific semiconductor chip.
The attainment of micro-miniaturization has been achieved via advancements in specific semiconductor fabrication disciplines, such as photolithography, and dry etching. The use of advanced exposure cameras, as well as the development of more photosensitive photoresist materials, have allowed sub-micron features to be routinely achieved in masking photoresist layers. In addition the development of more advanced dry etching tools, and processes, have resulted in the successful transfer of the sub-micron images in the masking photoresist layers, to underlying semiconductor materials, such as silicon, silicon oxide, metal, and metal silicide. However in addition to the use of advanced semiconductor fabrication disciplines, specific components of the semiconductor device, have to be addressed to continue to successfully address the performance and cost objectives. For example, isolation regions, used to physically, and electrically, isolate devices, or device components, have been formed using field oxide regions, created via thermal oxidation procedures. Field oxide, (FOX), regions, are created via high temperature thermal oxidation, of specific regions of the semiconductor substrate. Areas of the semiconductor substrate, to be used for subsequent active device regions, are protected from the FOX oxidation process, via use of an oxidation resistant insulator mask, such as silicon nitride. However during the FOX oxidation procedure, a "birds beak" formation, or oxidation occurring under the edges of the masking insulator layer, is formed, reducing the amount of area allotted for the active device region. To accommodate "birds beak", a larger active device area has to designed, thus negatively influencing the objective of smaller chips, or reduced processing costs.
The deleterious effect of "birds beak", for FOX applications, has been addressed by the use of shallow trench isolation, (STI), as a replacement for the FOX isolation regions. STI features the creation of a shallow trench, in the semiconductor substrate, via conventional patterning procedures, followed by the filling of the shallow trench, with an insulator layer. Unwanted "birds beak" formation, is not encountered since STI is obtained without the use of oxidation procedures. However several concerns still exist, when using STI regions. For example the narrow width of the shallow trench, makes it difficult to fill with a chemically vapor deposited, (CVD), insulator layer, sometimes resulting in a seam, or void, in the insulator fill, in the center of the shallow trench. In addition CVD insulator layers, such as silicon oxide, have a high removal, or etch rate, in dilute, or buffered hydrofluoric acid solutions, and thus a silicon oxide fill, can be significantly recessed in the shallow trench, during subsequent procedures, such as pre-cleans used prior to metal deposition. This invention will teach a procedure for creating insulator filled, shallow trench isolation regions, in which a borophosphosilicate glass, (BPSG), layer, with specific concentrations of B.sub.2 O.sub.3, and P.sub.2 O.sub.5, in a silicon oxide layer, is used to fill the shallow trench. A subsequent high temperature anneal is then used to reflow the insulator fill, eliminating any seams or voids that may have existed after the CVD procedure. The use of this specific BPSG layer, exhibits a reduced removal rate in HF solutions, compared to silicon oxide counterparts, thus allowing dilute, or buffered HF, pre-clean procedures, to be performed, without significant recessing, in the shallow trench. In addition the ability of this specific BPSG layer, to getter, or tie up, mobile ions, such as sodium, potassium, or lithium, also allow more stable memory devices to be achieved. Prior art, such as Okazawa, in U.S. Pat. No. 5,208,179, describes the use of BPSG filled, deep trenches, in addition to the use of FOX isolation regions. That prior art also teaches a process sequence different than the present invention, in that the BPSG layer, in a deep trench region, is formed after the creation of FOX regions, and after the gate materials, such as polysilicon have been deposited, negating the gettering influence of BPSG on the covered gate insulator layer.